반도체 패터닝을 위한 사진 식각(포토리소그래피)

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Electronics & Semiconductors Global Industrial Scale $70 billion

개요

Photolithography is the core patterning process in semiconductor fabrication, using light to transfer circuit patterns onto silicon wafers through photoresist chemistry. Modern extreme ultraviolet (EUV) lithography at 13.5 nm wavelength enables features as small as 3 nm, allowing billions of transistors per chip. The process involves coating wafers with photoresist, exposure through a mask using DUV (193 nm) or EUV light, development, and pattern transfer via etching. Each chip requires 50-100 lithography steps.

화학 공정

A silicon wafer is spin-coated with chemically amplified photoresist (30-200 nm thick). The wafer is soft-baked, then exposed to 193 nm ArF excimer laser or 13.5 nm EUV light through a 4x reduction mask. Post-exposure bake activates the acid-catalyzed deprotection. The resist is developed in TMAH (tetramethylammonium hydroxide) solution, revealing the circuit pattern for subsequent etch or deposition.

Photoacid generator + hv (193 nm or 13.5 nm) → H⁺ (photoacid)
Protected polymer + H⁺ →[PEB, 100 degrees C] Deprotected polymer (soluble in TMAH developer) — acid catalytic amplification cycle

원자재

  • Chemically amplified photoresist — JSR, TOK, Shin-Etsu, Sumitomo specialty chemicals (Photosensitive patterning material)
  • TMAH developer (2.38% (CH₃)₄NOH) — Chemical synthesis (Photoresist developer)
  • PGMEA (propylene glycol monomethyl ether acetate) — Chemical synthesis (Resist solvent and edge bead remover)

최종 제품

  • Patterned semiconductor wafers — Microprocessors, memory, logic chips (3-7 nm node technology with EUV)
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Environmental Impact

Photolithography uses large quantities of ultra-pure water (UPW) and PGMEA solvent. PFC gases (C₂F₆, CF₄, SF₆) used in subsequent plasma etching are potent greenhouse gases with atmospheric lifetimes of thousands of years. The industry is investing in PFC capture and destruction.

안전 고려사항

최근 혁신

High-NA EUV lithography (0.55 NA) is enabling sub-2 nm features.
Metal oxide photoresists for EUV offer better etch resistance and resolution.
DSA (directed self-assembly) of block copolymers is being developed as a lithography augmentation technique.

더 보기: Electronics & Semiconductors

Frequently Asked Questions

What industry uses 반도체 패터닝을 위한 사진 식각(포토리소그래피)?
반도체 패터닝을 위한 사진 식각(포토리소그래피) is used in the electronics & semiconductors sector at global industrial scale scale.
What process is involved in 반도체 패터닝을 위한 사진 식각(포토리소그래피)?
A silicon wafer is spin-coated with chemically amplified photoresist (30-200 nm thick). The wafer is soft-baked, then exposed to 193 nm ArF excimer laser or 13.5 nm EUV light through a 4x reduction mask. Post-exposure bake activates the acid-catalyzed deprotection. The resist is developed in TMAH (t
What is the economic significance of 반도체 패터닝을 위한 사진 식각(포토리소그래피)?
반도체 패터닝을 위한 사진 식각(포토리소그래피) has a market value of $70 billion.
What is the environmental impact of 반도체 패터닝을 위한 사진 식각(포토리소그래피)?
Photolithography uses large quantities of ultra-pure water (UPW) and PGMEA solvent. PFC gases (C₂F₆, CF₄, SF₆) used in subsequent plasma etching are potent greenhouse gases with atmospheric lifetimes of thousands of years. The industry is investing in PFC capture and destruction.
What raw materials are used in 반도체 패터닝을 위한 사진 식각(포토리소그래피)?
The main raw materials include: Chemically amplified photoresist, TMAH developer (2.38% (CH₃)₄NOH), PGMEA (propylene glycol monomethyl ether acetate).